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SystemVerilog salaries in Schweiz

Average salary

$92.5–101.6K/ year

25th percentile

$92.2K

75th percentile

$101.8K

Based on

3 jobs

Salary by seniority

LevelAverageBoard baselinevs. board
Entry level$92.5–101.6K——

Other locations

GS

Geneva, Switzerland

3 jobs

$92.5–101.6K

Top skills

P

Python

31 jobs

$106.5–128.2K

DA

Data Analysis

12 jobs

$86.6–99.2K

C

C++

10 jobs

$119–134.9K

ML

Machine Learning

8 jobs

$106–136K

PM

Project Management

7 jobs

$107–120.3K

C

CI/CD

7 jobs

$105.2–135.3K

Related titles

RE

Research Engineer

6 jobs

$78.9–86.8K

AP

Applied Physicist

6 jobs

$113.2–117.8K

SE

Software Engineer

6 jobs

$107.8–122.4K

SO

Station Operations

6 jobs

$44.7–57.5K

R

Research

5 jobs

$43.9K

SE

Software Engineering

5 jobs

$143.1–189.8K